1. Field of the Invention
The present invention relates to a battery state monitoring circuit and a battery device that detect a voltage and an abnormality of a secondary battery, and more particularly, to a battery state monitoring circuit and a battery device that are capable of controlling charge by a charger even if a secondary battery voltage drops to around 0 V.
2. Description of the Related Art
A battery device is provided with a function of permitting/inhibiting the charge to a secondary battery when a charger is connected thereto in a state in which a voltage of the secondary battery extremely drops to around 0 V (see, for example, Japanese Patent Application Laid-open No. 2000-308266). Hereinafter, such a function is referred to as function of permitting/inhibiting 0 V charge.
FIG. 3 illustrates a circuit diagram of a battery device including a conventional battery state monitoring circuit. The battery device including the conventional battery state monitoring circuit includes a secondary battery 1, a charge/discharge control circuit 2 for monitoring a voltage of the secondary battery 1, a switch circuit 3 for controlling the charge and discharge of the secondary battery 1, external terminals 4 and 5 between which a charger 8 or a load 9 is to be connected, and a charge switch drive circuit 7. The charge switch drive circuit 7 includes a level shifter circuit 15, a P-type metal oxide semiconductor (PMOS) transistor 16, an N-type metal oxide semiconductor (NMOS) transistor 17, a resistor 18, an inverter circuit 26, a NOR circuit 25, a PMOS transistor 20, and an NMOS transistor 21. The switch circuit 3 includes a discharge switch 10 and a charge switch 11.
The battery device described above functions to permit the 0 V charge through the following operations.
The level shifter circuit 15 outputs High when its input signal is High, and outputs Low when its input signal is Low. The output of the level shifter circuit 15 is then input to the NOR circuit 25. The PMOS transistor 16, the NMOS transistor 17, and the resistive element 18 together form a battery voltage detection circuit. When the voltage of the secondary battery 1 drops to be lower than a threshold voltage of the PMOS transistor 16, the battery voltage detection circuit outputs Low so that a signal of High is input to the NOR circuit 25 via the inverter circuit 26. The output of the NOR circuit 25 drives the charge switch 11 via an inversion output circuit formed of the PMOS transistor 20 and the NMOS transistor 21.
When the output of the level shifter circuit 15 is Low and the output of the battery voltage detection circuit is High, the output of the inverter circuit 26 is Low, and accordingly both the inputs of the NOR circuit 25 are Low and the output of the NOR circuit 25 is High. Therefore, a gate voltage of the charge switch 11 becomes Low to disable the charge.
In other cases than the above, the output of the NOR circuit 25 is Low, and hence the gate voltage of the charge switch 11 becomes High to permit the charge. Therefore, when the voltage of the secondary battery 1 becomes close to 0 V, the charge switch drive circuit 7 permits the charge. In other words, the battery device functions to permit the 0 V charge.
In the conventional technology, however, the above-mentioned charge/discharge control circuit 2 is driven at the voltage of the secondary battery 1, and hence there is a fear that a discharge control output terminal 12 may output High when the voltage of the secondary battery 1 is low, which poses the following disadvantages.
If the charger 8 is connected when the voltage of the secondary battery 1 is close to 0 V, the NMOS transistor 17 is turned ON, and a voltage of a charge control output terminal 13 becomes High to turn ON the charge switch 11. Then, a charge current flows into the secondary battery 1 from the charger 8. Because the charge/discharge control circuit 2 is driven at the voltage of the secondary battery 1, the output signal thereof remains indefinite until the charge/discharge control circuit 2 is allowed to operate. Accordingly, there is a fear that High may be output from the discharge control output terminal 12. Therefore, if the discharge control output terminal 12 outputs High while the charge switch drive circuit 7 is permitting the charge, the charge switch 11 is turned ON and the discharge switch 10 is also turned ON, with the result that a negative terminal of the secondary battery 1 and the external terminal 5 have substantially the same potential and the NMOS transistor 17 is turned OFF. Once the NMOS transistor 17 is turned OFF, the charge switch drive circuit 7 cancels permission of the charge. Therefore, there arises a problem of oscillation of alternately permitting and inhibiting the charge.